The invention relates to a decoding unit for CMI-encoded input signals having an input and an output, the input of the decoding unit being coupled via a time delay stage to a first input of a first gate circuit a second input of which is connected to the input of the decoding unit, the output of the gate circuit being coupled to the output of the decoding unit.
In a digital multiplex transmission system of the type described in, for example, Netherlands Patent Application No. 8203110, a digital signal is applied at the transmitter end to a CMI-encoding unit in which the digital signal is converted into the CMI-code format (coded mark inversion) recommended for the bit rate. The CMI-code is a two-level code, in which a logic 0 bit is encoded such that each of the two levels is present during half a bit time interval, first one and then the other level. A logic 1 bit is encoded by one of the two levels during an entire bit interval, more specifically such that the level alternates for consecutive logic 1 bits. At the receiver of the CMI-interface the digital channel includes a CMI decoding unit in which, after equalization and regeneration with the aid of the recovered system clock, the received CMI-encoded signal is converted into the normal binary code. The original composite digital signal with the nominal bit rate and the original system clock are then available at the output of the CMI-decoding unit.
In current decoding units of the above-defined type, as, for example, disclosed in the European patent application No. 0,208,558, the time delay stage is constituted by a bistable element producing a delay of half a bit interval. The gate circuit is constituted by an exclusive-OR gate. The CMI-encoded input signal and the delayed version thereof are each applied to an input of the exclusive-NOR gate. The output signal of the exclusive-NOR gate contains the appropriate information as regards the binary data during the second half of each bit interval. In the first half of each bit interval the data then occurring is undefined and assumes at random one of the logic values 0 or 1.
Often, from the point of view of bandwidth limitation, the exclusive NOR gate output signal is applied to the D-input of a D-flip-flop to whose clock input a read clock signal is applied. Since in the first half of each bit interval the data then occurring is undefined, it is necessary for the read clock signal to be word-synchronous with the 2-bit words in the CMI-encoded input signal. This has the disadvantage that an additional synchronizing circuit is required to realise this.